The present invention is directed generally to the transfer of data in a data processing system, and more particularly to a method and apparatus that provides fault tolerant error correcting code generation and detection.
Recognition of the phenomena that if anything can go wrong it will have given rise to error detecting and error correcting codes. Most error detection and correction techniques in use today rely upon one or more forms of "redundancy," extra bits that are an error detection or error correction code and are transmitted along with the informational data. The extra bit or bits can be used to detect errors that may have occurred in the informational bits. Data transmitted in this form, is received and, using the extra bits, checked to determine if the data was corrupted during transmission. If an error occurs, the data can be retransmitted.
Unfortunately, retransmitting the data is not entirely satisfactory. Not only are the additional time and increased complexity of the system (by implementing the necessary two way signalling used to conduct retransmission techniques problems), but if the data is recorded with the error, no amount of retransmission will overcome the problem.
If the redundancy is sufficient, the extra bits can be used to provide error correction to overcome certain of these problems.
In fault tolerant architecture, based upon the philosophy of no single point of failure, the error code generating and checking circuitry is usually duplicated, and operated in "lock step" to provide the fault tolerant capability. Often, one of the circuits are designed solely to perform the error correcting and detecting operations, while the other circuit functions only to check the first. If the first fails, the entire unit fails. If, for one reason or another, both circuits operate incorrectly, the error will never be discovered.